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º;ÈÖj½aclkhclksclk ”g ilm Zcoreaxiahbvop@ff930000rockchip,rk3288-vop ÿÿ“œÿ“ º;žѽaclk_vopdclk_vophclk_vop ”g def Zaxiahbdclk ¢hÉokayporth endpoint@0ÿ ©ih~endpoint@1ÿ ©jhyendpoint@2ÿ ©khrendpoint@3ÿ ©lhuiommu@ff930300rockchip,iommuÿÿ“ º Úvopb_mmu;ÅÑ ½aclkiface ”g  lÉokayhhvop@ff940000rockchip,rk3288-vop ÿÿ”œÿ” º;Æ¿Ò½aclk_vopdclk_vophclk_vop ”g °±² Zaxiahbdclk ¢mÉokayporth endpoint@0ÿ ©nhendpoint@1ÿ ©ohzendpoint@2ÿ ©phsendpoint@3ÿ ©qhviommu@ff940300rockchip,iommuÿÿ” º Úvopl_mmu;ÆÒ ½aclkiface ”g  lÉokayhmmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsiÿÿ–@ º;~d ½refpclk ”g „D Édisabledportsportendpoint@0ÿ ©rhkendpoint@1ÿ ©shplvds@ff96c000rockchip,rk3288-lvdsÿÿ–À@;g ½pclk_lvdslcdc(t ”g „D Édisabledportsport@0ÿendpoint@0ÿ ©uhlendpoint@1ÿ ©vhqdp@ff970000rockchip,rk3288-dpÿÿ—@ ºb;ic½dppclkêwïdpoZdp„DÉokaydefault(xportsport@0ÿendpoint@0ÿ ©yhjendpoint@1ÿ ©zhoport@1ÿendpoint@0ÿ ©{h«hdmi@ff980000rockchip,rk3288-dw-hdmiÿÿ˜î &„D ºg;hmn½iahbisfrcec ”g Éokaydefaultunwedge(|Z}h¢portsportendpoint@0ÿ ©~hiendpoint@1ÿ ©hnvideo-codec@ff9a0000rockchip,rk3288-vpuÿÿšº   Úvepuvdpu;ÐÜ ½aclkhclk ¢€ ”g iommu@ff9a0800rockchip,iommuÿÿš º Úvpu_mmu;ÐÜ ½aclkiface l ”g h€iommu@ff9c0440rockchip,iommu ÿÿœ@@ÿœ€@ ºo Úhevc_mmu;ÏÛ ½aclkiface l Édisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760ÿÿ£$º Újobmmugpu;À  ”g Éokay ¹‚hAgpu-opp-tableoperating-points-v2hopp-100000000{õá‚~ðopp-200000000{ ë‚~ðopp-300000000{ᣂB@opp-400000000{ׄ‚Èàopp-600000000{#ÃF‚Ðqos@ffaa0000sysconÿÿª h`qos@ffaa0080sysconÿÿª€ haqos@ffad0000sysconÿÿ­ hUqos@ffad0100sysconÿÿ­ hVqos@ffad0180sysconÿÿ­€ hWqos@ffad0400sysconÿÿ­ hXqos@ffad0480sysconÿÿ­€ hYqos@ffad0500sysconÿÿ­ hTqos@ffad0800sysconÿÿ­ hZqos@ffad0880sysconÿÿ­€ h[qos@ffad0900sysconÿÿ­ h\qos@ffae0000sysconÿÿ® h_qos@ffaf0000sysconÿÿ¯ h]qos@ffaf0080sysconÿÿ¯€ h^efuse@ffb40000rockchip,rk3288-efuseÿÿ´ ;q ½pclk_efusecpu-id@7ÿcpu_leakage@17ÿinterrupt-controller@ffc01000 arm,gic-400 Å Ú@ÿÿÀÿÀ ÿÀ@ ÿÀ`  º hpinctrlrockchip,rk3288-pinctrl„Dædefaultsleep(ƒ„…†‡Zƒ„…ˆ‰gpio0@ff750000rockchip,gpio-bankÿÿu ºQ;@ ë û Å Úç PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh1gpio1@ff780000rockchip,gpio-bankÿÿx ºR;A ë û Å Úgpio2@ff790000rockchip,gpio-bankÿÿy ºS;B ë û Å ÚM CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENh”gpio3@ff7a0000rockchip,gpio-bankÿÿz ºT;C ë û Å Ú‚ FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bankÿÿ{ ºU;D ë û Å Ú³ UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEh—gpio5@ff7c0000rockchip,gpio-bankÿÿ| ºV;E ë û Å ÚA SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhšgpio6@ff7d0000rockchip,gpio-bankÿÿ} ºW;F ë û Å Ú° I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhNgpio7@ff7e0000rockchip,gpio-bankÿÿ~ ºX;G ë û Å Úâ LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio8@ff7f0000rockchip,gpio-bankÿÿ ºY;H ë û Å Ú^ RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 Šhdmi-cec-c7 Šhdmi-ddc ŠŠh|hdmi-ddc-unwedge ‹Šh}vcc50-hdmi-en Šh›pcfg-output-low %h‹pcfg-pull-up 0hŒpcfg-pull-down =hpcfg-pull-none LhŠpcfg-pull-none-12ma L Y hsleepglobal-pwroff Šh…ddrio-pwroff Šh„ddr0-retention Œhƒddr1-retention Œedpedp-hpd  hxi2c0i2c0-xfer ŠŠhHi2c1i2c1-xfer ŠŠh.i2c2i2c2-xfer  Š ŠhMi2c3i2c3-xfer ŠŠh/i2c4i2c4-xfer ŠŠh0i2c5i2c5-xfer ŠŠh5i2s0i2s0-bus` ŠŠŠŠŠŠhflcdclcdc-ctl@ ŠŠŠŠhtsdmmcsdmmc-clk Žhsdmmc-cmd Žhsdmmc-cd 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#address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplypinctrl-namespinctrl-0wp-gpioscap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabledisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type