� ��8`(�(%digilent,zynq-zybo-z7xlnx,zynq-7000&Zynq ZYBO Z7 Development Boardcpuscpu@0arm,cortex-a9,cpu8<C�Q] ,+B@B@cpu@1arm,cortex-a9,cpu8<fpga-full fpga-regionnwpmu@f8891000arm,cortex-a9-pmu~�8����0fixedregulatorregulator-fixed�VCCPINT�B@�B@���amba simple-bus�wadc@f8007100xlnx,zynq-xadc-1.00.a8�q  ~�< can@e0008000xlnx,zynq-can-1.0 disabled<$ can_clkpclk8�� ~�@(@can@e0009000xlnx,zynq-can-1.0 disabled<% can_clkpclk8�� ~3�@(@gpio@e000a000xlnx,zynq-gpio-1.06<*BRg� ~8���i2c@e0004000cdns,i2c-r1p10 disabled<&� ~8�@i2c@e0005000cdns,i2c-r1p10 disabled<'� ~08�Pinterrupt-controller@f8f01000arm,cortex-a9-gicgR8�����cache-controller@f8f02000arm,pl310-cache8��  ~ x ���memory-controller@f8006000xlnx,zynq-ddrc-a058�`serial@e0000000xlnx,xuartpscdns,uart-r1p8 disabled<(uart_clkpclk8� ~serial@e0001000xlnx,xuartpscdns,uart-r1p8okay<)uart_clkpclk8� ~2spi@e0006000xlnx,zynq-spi-r1p68�` disabled� ~<" ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p68�p disabled� ~1<# ref_clkpclkethernet@e000b000cdns,zynq-gemcdns,gem8��okay ~< pclkhclktx_clk �rgmii-id�ethernet-phy@08 ,ethernet-phy�ethernet@e000c000cdns,zynq-gemcdns,gem8�� disabled ~-<pclkhclktx_clksdhci@e0100000arasan,sdhci-8.9aokayclk_xinclk_ahb< � ~8�sdhci@e0101000arasan,sdhci-8.9a disabledclk_xinclk_ahb<!� ~/8�slcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd8�w�clkc@100�xlnx,ps7-clkc�j�armpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb8���U�rstc@200xlnx,zynq-reset8Hpinctrl@700xlnx,pinctrl-zynq8dmac@f8003000arm,pl330arm,primecell8�0�.abortdma0dma1dma2dma3dma4dma5dma6dma7l~ ()*+(3A< apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.08�p� ~< ref_clk�timer@f8f00200arm,cortex-a9-global-timer8��  ~ �<timer@f8001000�$~    cdns,ttc<8�timer@f8002000�$~%&' cdns,ttc<8� timer@f8f00600� ~ arm,cortex-a9-twd-timer8�� <usb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2okay<� ~8� OulpiXhost`usb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2 disabled<� ~,8�0Oulpiwatchdog@f8005000<-cdns,wdt-r1p2� ~ 8�Ph aliasest/amba/ethernet@e000b000~/amba/serial@e0001000memory@0,memory8 chosen��serial0:115200n8phy0�usb-nop-xceiv �.� #address-cells#size-cellscompatiblemodeldevice_typeregclocksclock-latencycpu0-supplyoperating-pointsfpga-mgrrangesinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onphandlestatusclock-namestx-fifo-depthrx-fifo-depth#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellsarm,data-latencyarm,tag-latencycache-unifiedcache-levelphy-modephy-handle#clock-cellsfclk-enableclock-output-namesps-clk-frequency#reset-cellssysconinterrupt-names#dma-cells#dma-channels#dma-requestsphy_typedr_modeusb-phytimeout-secethernet0serial0bootargsstdout-path#phy-cellsreset-gpios