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EO€O€™pSׄZopp@400000000,1250 EÐЙpSׄZopp@416000000,1200 EO€O€™pS˨Zopp@416000000,1250 EÐЙpS˨Zopp@450000000,1200 EO€O€™pSÒt€Zopp@450000000,1250 EÐЙpSÒt€Zopp@533000000,1200 EO€O€™pSÄï@Zopp@533000000,1250 EÐЙpSÄï@Zopp@625000000,1200 EO€O€™pS%@¾@Zopp@625000000,1250 EÐЙpS%@¾@Zopp@667000000,1200 EO€O€™pS'ÁœÀZopp@750000000,1300 EÖ Ö ™pS,´€Zopp@800000000,1300 EÖ Ö ™pS/¯Zopp@900000000,1350 E™p™p™pS5¤éZemc-bandwidth-opp-tableoperating-points-v2= opp@12750000SÂŒ°ZwŽpopp@25500000S…`Zwàopp@27000000S›üÀZwKÀopp@51000000S 2ÀZw9Àopp@54000000S7ù€Zw—€opp@102000000Se€Zw s€opp@108000000SoóZw /opp@204000000S (ËZwçkopp@333500000SàÎ`Zw(µàopp@375000000SZ ÀZw-ÆÀopp@400000000SׄZw0Ôopp@416000000S˨Zw2Èopp@450000000SÒt€Zw6î€opp@533000000SÄï@ZwA@opp@625000000S%@¾@ZwLK@opp@667000000S'ÁœÀZwQkÀopp@750000000S,´€Zw[€opp@800000000S/¯Zwa¨opp@900000000S5¤éZwmÝmemory@80000000…memory‘€ðpcie@3000nvidia,tegra30-pcie…pci‘08 •padsaficsŸbc ªintrmsiºË Þbìÿ+ö@@ B(( ýFHÁ×pexafipll_ecmlFHJpexafipcie_x#okay*+;<L`q†pci@1,0…pci–‚‘ìÿ#okay+ö©pci@2,0…pci–‚‘ìÿ #disabled+ö©pci@3,0…pci–‚@‘ìÿ#okay+ö©sram@40000000 mmio-sram‘@+ ö@sram@400‘üº=host1x@50000000nvidia,tegra30-host1x‘P@ŸACªsyncpthost1xýhost1xhost1x¿ + öTTmpe@54040000nvidia,tegra30-mpe‘T ŸDý<<mpe¿vi@54080000nvidia,tegra30-vi‘T ŸEý¤vi¿epp@540c0000nvidia,tegra30-epp‘T  ŸFýepp¿isp@54100000nvidia,tegra30-isp‘T ŸGýisp¿gr2d@54140000nvidia,tegra30-gr2d‘T ŸHý2d¿gr3d@54180000nvidia,tegra30-gr3d‘Týb3d3d2b3d3d2¿  dc@54200000nvidia,tegra30-dc‘T  ŸIý³ dcparentdc¿Æ<Ò#àwinawinbwinb-vfilterwinccursorrgb #disableddc@54240000nvidia,tegra30-dc‘T$ ŸJý³ dcparentdc¿Æ<Ò#àwinawinbwinb-vfilterwinccursorrgb #disabledhdmi@54280000nvidia,tegra30-hdmi‘T( ŸKý3½ hdmiparent3hdmi#okayó ÿU   o tvo@542c0000nvidia,tegra30-tvo‘T, ŸLý© #disableddsi@54300000nvidia,tegra30-dsi‘T0ý0» dsiparent0dsi #disableddsi@54400000nvidia,tegra30-dsi‘T@ýR» dsiparentTdsi #disabledtimer@50040600arm,cortex-a9-twd-timer‘P   Ÿ ýÖinterrupt-controller@50041000arm,cortex-a9-gic‘PP-º =cache-controller@50043000arm,pl310-cache‘P0 B Scqinterrupt-controller@60004000nvidia,tegra30-ictlr(‘`@`AP`BP`CP`DP-º =timer@60005000*nvidia,tegra30-timernvidia,tegra20-timer‘`PHŸ)*yzýclock@60006000nvidia,tegra30-car‘``}Š=flow-controller@60007000nvidia,tegra30-flowctrl‘`pdma@6000a000,nvidia,tegra30-apbdmanvidia,tegra20-apbdma‘` €Ÿhijklmnopqrstuvw€‚ƒ„…†‡ˆ‰Š‹ŒŽý""dma—=ahb@6000c000nvidia,tegra30-ahb‘`ÀPactmon@6000c800nvidia,tegra30-actmon‘`È Ÿ-ýw9 actmonemcwactmon¢  Ò' àcpu-read¶gpio@6000d000nvidia,tegra30-gpio‘`Ð`Ÿ !"#7WY}ÅѺ-= vde@6001a000&nvidia,tegra30-vdenvidia,tegra20-vdeH‘` `°`À`Â`Ä`Æ`È`Ê`Ø*•sxebsevmbeppemcetfeppbvdmaframeidá$Ÿ   ªsync-tokenbsevsxeý=vdemc=¿apbmisc@70000800.nvidia,tegra30-apbmiscnvidia,tegra20-apbmisc‘pdppinmux@70000868nvidia,tegra30-pinmux‘phÔp0äædefaultôpinmux=clk_32k_out_pa0þclk_32k_out_pa0 blink&6uart3_cts_n_pa1þuart3_cts_n_pa1 uartc&6dap2_fs_pa2 þdap2_fs_pa2 i2s1&6dap2_sclk_pa3þdap2_sclk_pa3 i2s1&6dap2_din_pa4 þdap2_din_pa4 i2s1&6dap2_dout_pa5þdap2_dout_pa5 i2s1&6sdmmc3_clk_pa6þsdmmc3_clk_pa6 sdmmc3&6sdmmc3_cmd_pa7þsdmmc3_cmd_pa7 sdmmc3&6gmi_a17_pb0 þgmi_a17_pb0 spi4&6gmi_a18_pb1 þgmi_a18_pb1 spi4&6lcd_pwr0_pb2 þlcd_pwr0_pb2  displaya&6lcd_pclk_pb3 þlcd_pclk_pb3  displaya&6sdmmc3_dat3_pb4þsdmmc3_dat3_pb4 sdmmc3&6sdmmc3_dat2_pb5þsdmmc3_dat2_pb5 sdmmc3&6sdmmc3_dat1_pb6þsdmmc3_dat1_pb6 sdmmc3&6sdmmc3_dat0_pb7þsdmmc3_dat0_pb7 sdmmc3&6uart3_rts_n_pc0þuart3_rts_n_pc0 uartc&6lcd_pwr1_pc1 þlcd_pwr1_pc1  displaya&6uart2_txd_pc2þuart2_txd_pc2 uartb&6uart2_rxd_pc3þuart2_rxd_pc3 uartb&6gen1_i2c_scl_pc4þgen1_i2c_scl_pc4 i2c1&6Jgen1_i2c_sda_pc5þgen1_i2c_sda_pc5 i2c1&6Jlcd_pwr2_pc6 þlcd_pwr2_pc6  displaya&6gmi_wp_n_pc7 þgmi_wp_n_pc7 gmi&6sdmmc3_dat5_pd0þsdmmc3_dat5_pd0 sdmmc3&6sdmmc3_dat4_pd1þsdmmc3_dat4_pd1 sdmmc3&6lcd_dc1_pd2 þlcd_dc1_pd2  displaya&6sdmmc3_dat6_pd3þsdmmc3_dat6_pd3 spdif&6sdmmc3_dat7_pd4þsdmmc3_dat7_pd4 spdif&6vi_d1_pd5 þvi_d1_pd5 sdmmc2&6vi_vsync_pd6 þvi_vsync_pd6 ddr&6vi_hsync_pd7 þvi_hsync_pd7 ddr&6lcd_d0_pe0 þlcd_d0_pe0  displaya&6lcd_d1_pe1 þlcd_d1_pe1  displaya&6lcd_d2_pe2 þlcd_d2_pe2  displaya&6lcd_d3_pe3 þlcd_d3_pe3  displaya&6lcd_d4_pe4 þlcd_d4_pe4  displaya&6lcd_d5_pe5 þlcd_d5_pe5  displaya&6lcd_d6_pe6 þlcd_d6_pe6  displaya&6lcd_d7_pe7 þlcd_d7_pe7  displaya&6lcd_d8_pf0 þlcd_d8_pf0  displaya&6lcd_d9_pf1 þlcd_d9_pf1  displaya&6lcd_d10_pf2 þlcd_d10_pf2  displaya&6lcd_d11_pf3 þlcd_d11_pf3  displaya&6lcd_d12_pf4 þlcd_d12_pf4  displaya&6lcd_d13_pf5 þlcd_d13_pf5  displaya&6lcd_d14_pf6 þlcd_d14_pf6  displaya&6lcd_d15_pf7 þlcd_d15_pf7  displaya&6gmi_ad0_pg0 þgmi_ad0_pg0 nand&6gmi_ad1_pg1 þgmi_ad1_pg1 nand&6gmi_ad2_pg2 þgmi_ad2_pg2 nand&6gmi_ad3_pg3 þgmi_ad3_pg3 nand&6gmi_ad4_pg4 þgmi_ad4_pg4 nand&6gmi_ad5_pg5 þgmi_ad5_pg5 nand&6gmi_ad6_pg6 þgmi_ad6_pg6 nand&6gmi_ad7_pg7 þgmi_ad7_pg7 nand&6gmi_ad8_ph0 þgmi_ad8_ph0 pwm0&6gmi_ad9_ph1 þgmi_ad9_ph1 pwm1&6gmi_ad10_ph2 þgmi_ad10_ph2 nand&6gmi_ad11_ph3 þgmi_ad11_ph3 nand&6gmi_ad12_ph4 þgmi_ad12_ph4 nand&6gmi_ad13_ph5 þgmi_ad13_ph5 nand&6gmi_ad14_ph6 þgmi_ad14_ph6 nand&6gmi_wr_n_pi0 þgmi_wr_n_pi0 nand&6gmi_oe_n_pi1 þgmi_oe_n_pi1 nand&6gmi_dqs_pi2 þgmi_dqs_pi2 nand&6gmi_iordy_pi5þgmi_iordy_pi5 rsvd1&6gmi_cs7_n_pi6þgmi_cs7_n_pi6 nand&6gmi_wait_pi7 þgmi_wait_pi7 nand&6lcd_de_pj1 þlcd_de_pj1  displaya&6lcd_hsync_pj3þlcd_hsync_pj3  displaya&6lcd_vsync_pj4þlcd_vsync_pj4  displaya&6uart2_cts_n_pj5þuart2_cts_n_pj5 uartb&6uart2_rts_n_pj6þuart2_rts_n_pj6 uartb&6gmi_a16_pj7 þgmi_a16_pj7 spi4&6gmi_adv_n_pk0þgmi_adv_n_pk0 nand&6gmi_clk_pk1 þgmi_clk_pk1 nand&6gmi_cs2_n_pk3þgmi_cs2_n_pk3 rsvd1&6gmi_cs3_n_pk4þgmi_cs3_n_pk4 nand&6spdif_out_pk5þspdif_out_pk5 spdif&6spdif_in_pk6 þspdif_in_pk6 spdif&6gmi_a19_pk7 þgmi_a19_pk7 spi4&6vi_d2_pl0 þvi_d2_pl0 sdmmc2&6vi_d3_pl1 þvi_d3_pl1 sdmmc2&6vi_d4_pl2 þvi_d4_pl2 vi&6vi_d5_pl3 þvi_d5_pl3 sdmmc2&6vi_d6_pl4 þvi_d6_pl4 vi&6vi_d7_pl5 þvi_d7_pl5 sdmmc2&6vi_d8_pl6 þvi_d8_pl6 sdmmc2&6vi_d9_pl7 þvi_d9_pl7 sdmmc2&6lcd_d16_pm0 þlcd_d16_pm0  displaya&6lcd_d17_pm1 þlcd_d17_pm1  displaya&6lcd_d18_pm2 þlcd_d18_pm2  displaya&6lcd_d19_pm3 þlcd_d19_pm3  displaya&6lcd_d20_pm4 þlcd_d20_pm4  displaya&6lcd_d21_pm5 þlcd_d21_pm5  displaya&6lcd_d22_pm6 þlcd_d22_pm6  displaya&6lcd_d23_pm7 þlcd_d23_pm7  displaya&6dap1_fs_pn0 þdap1_fs_pn0 i2s0&6dap1_din_pn1 þdap1_din_pn1 i2s0&6dap1_dout_pn2þdap1_dout_pn2 i2s0&6dap1_sclk_pn3þdap1_sclk_pn3 i2s0&6lcd_cs0_n_pn4þlcd_cs0_n_pn4  displaya&6lcd_sdout_pn5þlcd_sdout_pn5  displaya&6lcd_dc0_pn6 þlcd_dc0_pn6  displaya&6hdmi_int_pn7 þhdmi_int_pn7 hdmi&6ulpi_data7_po0þulpi_data7_po0 uarta&6ulpi_data0_po1þulpi_data0_po1 uarta&6ulpi_data1_po2þulpi_data1_po2 uarta&6ulpi_data2_po3þulpi_data2_po3 uarta&6ulpi_data3_po4þulpi_data3_po4 uarta&6ulpi_data4_po5þulpi_data4_po5 uarta&6ulpi_data5_po6þulpi_data5_po6 uarta&6ulpi_data6_po7þulpi_data6_po7 uarta&6dap3_fs_pp0 þdap3_fs_pp0 i2s2&6dap3_din_pp1 þdap3_din_pp1 i2s2&6dap3_dout_pp2þdap3_dout_pp2 i2s2&6dap3_sclk_pp3þdap3_sclk_pp3 i2s2&6dap4_fs_pp4 þdap4_fs_pp4 i2s3&6dap4_din_pp5 þdap4_din_pp5 i2s3&6dap4_dout_pp6þdap4_dout_pp6 i2s3&6dap4_sclk_pp7þdap4_sclk_pp7 i2s3&6kb_col0_pq0 þkb_col0_pq0 kbc&6kb_col1_pq1 þkb_col1_pq1 kbc&6kb_col2_pq2 þkb_col2_pq2 kbc&6kb_col3_pq3 þkb_col3_pq3 kbc&6kb_col4_pq4 þkb_col4_pq4 kbc&6kb_col5_pq5 þkb_col5_pq5 kbc&6kb_col6_pq6 þkb_col6_pq6 kbc&6kb_col7_pq7 þkb_col7_pq7 kbc&6kb_row0_pr0 þkb_row0_pr0 kbc&6kb_row1_pr1 þkb_row1_pr1 kbc&6kb_row2_pr2 þkb_row2_pr2 kbc&6kb_row3_pr3 þkb_row3_pr3 kbc&6kb_row4_pr4 þkb_row4_pr4 kbc&6kb_row5_pr5 þkb_row5_pr5 kbc&6kb_row6_pr6 þkb_row6_pr6 kbc&6kb_row7_pr7 þkb_row7_pr7 kbc&6kb_row8_ps0 þkb_row8_ps0 kbc&6kb_row9_ps1 þkb_row9_ps1 kbc&6kb_row10_ps2 þkb_row10_ps2 kbc&6kb_row11_ps3 þkb_row11_ps3 kbc&6kb_row12_ps4 þkb_row12_ps4 kbc&6kb_row13_ps5 þkb_row13_ps5 kbc&6kb_row14_ps6 þkb_row14_ps6 kbc&6kb_row15_ps7 þkb_row15_ps7 kbc&6vi_pclk_pt0 þvi_pclk_pt0 rsvd1&6vi_mclk_pt1 þvi_mclk_pt1 vi&6vi_d10_pt2 þvi_d10_pt2 ddr&6vi_d11_pt3 þvi_d11_pt3 ddr&6vi_d0_pt4 þvi_d0_pt4 ddr&6gen2_i2c_scl_pt5þgen2_i2c_scl_pt5 i2c2&6Jgen2_i2c_sda_pt6þgen2_i2c_sda_pt6 i2c2&6Jsdmmc4_cmd_pt7þsdmmc4_cmd_pt7 sdmmc4&6pu0þpu0 owr&6pu1þpu1 rsvd1&6pu2þpu2 rsvd1&6pu3þpu3 pwm0&6pu4þpu4 pwm1&6pu5þpu5 pwm2&6pu6þpu6 pwm3&6jtag_rtck_pu7þjtag_rtck_pu7 rtck&6pv0þpv0 rsvd1&6pv2þpv2 owr&6pv3þpv3  clk_12m_out&6ddc_scl_pv4 þddc_scl_pv4 i2c4&6ddc_sda_pv5 þddc_sda_pv5 i2c4&6crt_hsync_pv6þcrt_hsync_pv6 crt&6crt_vsync_pv7þcrt_vsync_pv7 crt&6lcd_cs1_n_pw0þlcd_cs1_n_pw0  displaya&6lcd_m1_pw1 þlcd_m1_pw1  displaya&6spi2_cs1_n_pw2þspi2_cs1_n_pw2 spi2&6clk1_out_pw4 þclk1_out_pw4  extperiph1&6clk2_out_pw5 þclk2_out_pw5  extperiph2&6uart3_txd_pw6þuart3_txd_pw6 uartc&6uart3_rxd_pw7þuart3_rxd_pw7 uartc&6spi2_sck_px2 þspi2_sck_px2 gmi&6spi1_mosi_px4þspi1_mosi_px4 spi1&6spi1_sck_px5 þspi1_sck_px5 spi1&6spi1_cs0_n_px6þspi1_cs0_n_px6 spi1&6spi1_miso_px7þspi1_miso_px7 spi1&6ulpi_clk_py0 þulpi_clk_py0 uartd&6ulpi_dir_py1 þulpi_dir_py1 uartd&6ulpi_nxt_py2 þulpi_nxt_py2 uartd&6ulpi_stp_py3 þulpi_stp_py3 uartd&6sdmmc1_dat3_py4þsdmmc1_dat3_py4 sdmmc1&6sdmmc1_dat2_py5þsdmmc1_dat2_py5 sdmmc1&6sdmmc1_dat1_py6þsdmmc1_dat1_py6 sdmmc1&6sdmmc1_dat0_py7þsdmmc1_dat0_py7 sdmmc1&6sdmmc1_clk_pz0þsdmmc1_clk_pz0 sdmmc1&6sdmmc1_cmd_pz1þsdmmc1_cmd_pz1 sdmmc1&6lcd_sdin_pz2 þlcd_sdin_pz2  displaya&6lcd_wr_n_pz3 þlcd_wr_n_pz3  displaya&6lcd_sck_pz4 þlcd_sck_pz4  displaya&6sys_clk_req_pz5þsys_clk_req_pz5 sysclk&6pwr_i2c_scl_pz6þpwr_i2c_scl_pz6 i2cpwr&6Jpwr_i2c_sda_pz7þpwr_i2c_sda_pz7 i2cpwr&6Jsdmmc4_dat0_paa0þsdmmc4_dat0_paa0 sdmmc4&6sdmmc4_dat1_paa1þsdmmc4_dat1_paa1 sdmmc4&6sdmmc4_dat2_paa2þsdmmc4_dat2_paa2 sdmmc4&6sdmmc4_dat3_paa3þsdmmc4_dat3_paa3 sdmmc4&6sdmmc4_dat4_paa4þsdmmc4_dat4_paa4 sdmmc4&6sdmmc4_dat5_paa5þsdmmc4_dat5_paa5 sdmmc4&6sdmmc4_dat6_paa6þsdmmc4_dat6_paa6 sdmmc4&6sdmmc4_dat7_paa7þsdmmc4_dat7_paa7 sdmmc4&6pbb0þpbb0 i2s4&6cam_i2c_scl_pbb1þcam_i2c_scl_pbb1 i2c3&6Jcam_i2c_sda_pbb2þcam_i2c_sda_pbb2 i2c3&6Jpbb3þpbb3 vgp3&6pbb4þpbb4 vgp4&6pbb5þpbb5 vgp5&6pbb6þpbb6 vgp6&6pbb7þpbb7 i2s4&6cam_mclk_pcc0þcam_mclk_pcc0 vi_alt3&6pcc1þpcc1 i2s4&6pcc2þpcc2 i2s4&6sdmmc4_rst_n_pcc3þsdmmc4_rst_n_pcc3 sdmmc4&6sdmmc4_clk_pcc4þsdmmc4_clk_pcc4 sdmmc4&6clk2_req_pcc5þclk2_req_pcc5 dap&6pex_l2_rst_n_pcc6þpex_l2_rst_n_pcc6 pcie&6pex_l2_clkreq_n_pcc7þpex_l2_clkreq_n_pcc7 pcie&6pex_l0_prsnt_n_pdd0þpex_l0_prsnt_n_pdd0 pcie&6pex_l0_rst_n_pdd1þpex_l0_rst_n_pdd1 pcie&6pex_l0_clkreq_n_pdd2þpex_l0_clkreq_n_pdd2 pcie&6pex_wake_n_pdd3þpex_wake_n_pdd3 pcie&6pex_l1_prsnt_n_pdd4þpex_l1_prsnt_n_pdd4 pcie&6pex_l1_rst_n_pdd5þpex_l1_rst_n_pdd5 pcie&6pex_l1_clkreq_n_pdd6þpex_l1_clkreq_n_pdd6 pcie&6pex_l2_prsnt_n_pdd7þpex_l2_prsnt_n_pdd7 pcie&6clk3_out_pee0þclk3_out_pee0  extperiph3&6clk3_req_pee1þclk3_req_pee1 dev3&6clk1_req_pee2þclk1_req_pee2 dap&6hdmi_cec_pee3þhdmi_cec_pee3 cec&6Jowrþowr owr&6sdio3 þdrive_sdio3\s‚.œ*´Ìgpv þdrive_gpvœserial@70006000(nvidia,tegra30-uartnvidia,tegra20-uart‘p`@å Ÿ$ýserialïôrxtx#okayserial@70006040(nvidia,tegra30-uartnvidia,tegra20-uart‘p`@@å Ÿ%ý serialï  ôrxtx #disabledserial@70006200(nvidia,tegra30-uartnvidia,tegra20-uart‘pbå Ÿ.ý77serialï  ôrxtx #disabledserial@70006300(nvidia,tegra30-uartnvidia,tegra20-uart‘pcå ŸZýAAserialïôrxtx #disabledserial@70006400(nvidia,tegra30-uartnvidia,tegra20-uart‘pdå Ÿ[ýBBserialïôrxtx #disabledgmi@70009000nvidia,tegra30-gmi‘p+öHÿÿÿý*gmi*gmi #disabledpwm@7000a000&nvidia,tegra30-pwmnvidia,tegra20-pwm‘p þýpwm #disabledrtc@7000e000&nvidia,tegra30-rtcnvidia,tegra20-rtc‘pà Ÿýi2c@7000c000&nvidia,tegra30-i2cnvidia,tegra20-i2c‘pÀ Ÿ&+ý ¶div-clkfast-clk i2cïôrxtx#okay † i2c@7000c400&nvidia,tegra30-i2cnvidia,tegra20-i2c‘pÄ ŸT+ý6¶div-clkfast-clk6i2cïôrxtx#okay † i2c@7000c500&nvidia,tegra30-i2cnvidia,tegra20-i2c‘pÅ Ÿ\+ýC¶div-clkfast-clkCi2cïôrxtx#okay † i2c@7000c700&nvidia,tegra30-i2cnvidia,tegra20-i2c‘pÇ Ÿx+ýg¶gi2cdiv-clkfast-clkïôrxtx#okay † = i2c@7000d000&nvidia,tegra30-i2cnvidia,tegra20-i2c‘pÐ Ÿ5+ý/¶div-clkfast-clk/i2cïôrxtx#okay † rt5640@1crealtek,rt5640‘ Ÿ»  º=#tps65911@2d ti,tps65911‘- ŸVº-/=ÅÑXdp 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regulator@3regulator-fixed ¹vdd_5v_sataÈLK@àLK@øxÿ   regulator@4regulator-fixed ¹usb1_vbusÈLK@àLK@ÿ  î  regulator@5regulator-fixed ¹usb3_vbusÈLK@àLK@ÿ  ì  =regulator@6regulator-fixed¹sys_3v3,vdd_3v3_alwÈ2Z à2Z øxÿ ! =regulator@7regulator-fixed ¹sys_3v3_pexsÈ2Z à2Z øxÿ  _ =regulator@8regulator-fixed ¹+VDD_5V_HDMIÈLK@àLK@øx = sound;nvidia,tegra-audio-rt5640-beavernvidia,tegra-audio-rt5640 -NVIDIA Tegra Beaver@ :HeadphonesHPORHeadphonesHPOLMic JackMICBIAS1IN2PMic Jack O" e# x ²ý¸¹$pll_apll_a_out0mclk Œx$ œ¹x compatibleinterrupt-parent#address-cells#size-cellsmodelphandleopp-microvoltopp-hzopp-supported-hwopp-suspendopp-peak-kBpsdevice_typeregreg-namesinterruptsinterrupt-names#interrupt-cellsinterrupt-map-maskinterrupt-mapbus-rangerangesclocksclock-namesresetsreset-namesstatusavdd-pexa-supplyavdd-pexb-supplyavdd-pex-pll-supplyavdd-plle-supplyvddio-pex-ctl-supplyhvdd-pex-supplyassigned-addressesnvidia,num-lanespooliommusnvidia,headinterconnectsinterconnect-nameshdmi-supplyvdd-supplynvidia,hpd-gpionvidia,ddc-i2c-businterrupt-controllerarm,data-latencyarm,tag-latencycache-unifiedcache-level#clock-cells#reset-cells#dma-cellsoperating-points-v2#cooling-cells#gpio-cellsgpio-controllerirampinctrl-namespinctrl-0nvidia,pinsnvidia,functionnvidia,pullnvidia,tristatenvidia,enable-inputnvidia,open-drainnvidia,high-speed-modenvidia,schmittnvidia,pull-down-strengthnvidia,pull-up-strengthnvidia,slew-rate-risingnvidia,slew-rate-fallingreg-shiftdmasdma-names#pwm-cellsclock-frequencyrealtek,ldo1-en-gpioswakeup-sourceti,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-coupled-withregulator-coupled-max-spreadregulator-max-step-microvoltnvidia,tegra-cpu-regulatorregulator-boot-onti,vsel0-state-highti,vsel1-state-highnvidia,tegra-core-regulatorspi-max-frequencynvidia,invert-interruptnvidia,suspend-modenvidia,cpu-pwr-good-timenvidia,cpu-pwr-off-timenvidia,core-pwr-good-timenvidia,core-pwr-off-timenvidia,core-power-req-active-highnvidia,sys-clock-req-active-high#iommu-cells#interconnect-cellsnvidia,memory-controllernvidia,ahub-cif-idsvqmmc-supplycd-gpioswp-gpiospower-gpiosbus-widthnon-removablephy_typenvidia,needs-double-resetnvidia,phydr_mode#phy-cellsnvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia,xcvr-setup-use-fusesnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,xcvr-hsslewnvidia,hssquelch-levelnvidia,hsdiscon-levelnvidia,has-utmi-pad-registersvbus-supplycpu-supplyinterrupt-affinityopp-sharedclock-latency-nsrtc0rtc1serial0stdout-pathlabelenable-active-highvin-supplygpio-open-drainnvidia,modelnvidia,audio-routingnvidia,i2s-controllernvidia,audio-codecnvidia,hp-det-gpiosassigned-clocksassigned-clock-parents